Detailed design
RTL synthesis
Electronic System Level design
Micro architecture
System Architecture
Design for Test
Prototyping and production support
HDL implementation
Verification
Physical design
Verification of ARM-based SoCs
Thorough third party IP qualification
Building state-of-the-art test benches using HVL (Specman, Vera, SystemVerilog), HDL (Verilog, VHDL), SW (C, C++, SystemC), scripting languages (Perl, TCL)
Reusable verification IP development
Proprietary FPGA platforms for rapid prototyping
Verification of communications, embedded, storage, processors and consumer ASIC / SoC designs
Test system build and verification management
Expertise in silicon validation
Migration of legacy test bench to new methodology
Design emulation